Photolithography is a process used in micro-fabrication to pattern the bulk of a substrate. It uses light to transfer a geometric pattern from an optical mask to a light-sensitive chemical “photoresist,” or simply “resist,” on the substrate. The pattern in the resist is created by exposing it to light with a projected image using an optical mask.
As semiconductor feature sizes continue to shrink further below the exposure wavelength, additional elements of the integrated circuit design become increasingly significant factors impacting the resulting integrated circuit (IC) chip. In addition, the cost of manufacturing advanced mask sets is steadily increasing as technology becomes more and more complex in addition to increasing turn-around time in semiconductor manufacturing. As a result, computer simulations of the photolithography process and the impact of accurate photolithography modeling becomes more important to ensure efficient and effective cost and time of IC chip manufacture.
Electronic Design Automation (EDA) software is a term for the collective tools supporting design and verification of IC chips. Some EDA tools create models of elements of the IC design for the photolithography process. Effective photolithography modeling includes capacitive or resistive effects of the elements of the IC design and the impact of their relative positions. Frequently, these effects are modeled in separate tools within EDA software. For example, the Synopsys (formerly Magma) tool family named QuickCap is a capacitance extractor. The QuickCap tool uses a geometry pre-processor named gds2cap to translate layout data into a 3D representation and reduced SPICE netlist with resistance and capacitance, among other tasks. A language named QTF is used by gds2cap. As another example, the Synopsys tool family named STAR is a similar capacitance extractor. A tool within STAR is used to translate layout data, using the ITF language. Other tools have solutions in this space, such as Avanti RCXT, Mentor Calibre, and Cadence Fire&Ice.
In an effort to aid in resolution of features in the semiconductor process, designers and fabricators have gone to a multi-exposure approach of photolithography. Within the same layer of an integrated circuit, two or more exposures are made using different portions of the IC design at that layer in an attempt to resolve smaller features more clearly. Specifically, that single layer will have multiple masks used to create the features within that layer. This is called multi-patterning. Unfortunately, existing techniques to accurately model capacitive or resistive effects of multi-patterning are inaccurate. EDA tool creators and fabricators have been trying to increase the accuracy of models to compensate for the effects of multi-patterning, but have not been successful thus far and do not match, for example, thicknesses in all patterns of a multi-pattern approach.